SOC Senior Physical Design Manager

Company: Intel
Location: Trenton
Posted on: March 20, 2023

Job Description:

Job Description
Come join a growing team working on innovative custom SoC designs. The project is in the early (pre-execution) design phase with plenty of opportunities for growth, leadership and technical career development. We are looking for talented individuals to be part of our high performing team in the physical design of highly complex blocks from synthesis/APR through post-layout verification, SoC integration, full-chip electrical verification and tape-in/tape-out. You will be part of the Custom Compute Group (XCC) within the Accelerated Computing Systems and Graphics Group (AXG) and we are chartered with providing custom and differentiated silicon/platform solutions to our customers for emerging use-cases, in adjacent as well as new market segments.
As a SoC Senior Engineer Manager in Intel's AXG/IFED group you will use your knowledge of physical design, integration and tapeout (including IP, integration, and full-chip aspects) to manage a large 50+ design team consisting of technical leaders and first level managers to deliver complex SOCs.
You will be responsible for, but not limited to:

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  Manage a team of physical design technical leads and managers leading the delivery of partitions, subsystems and SOC designs.
  
  
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  Manage the overall schedule and dependencies to enable timely delivery of the SOC.
  
  
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  Cross domain tracking and stakeholder management and feedback including architecture, logic design, product LZ requirements, environments, tools, and methodologies.
  
  
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  Responsible for managing the delivery of incoming collateral and quality including IP design collateral to enable physical design.
  
  
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  Collaborate with cross-functional teams to drive continuous improvement to both the design process, collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
  
  
  Behavioral Traits:
  
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  • Good communication skills.
    
    Qualifications
    Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
    Minimum Qualifications:
    Must have a Bachelor's in Computer/Electrical Engineering or related fields with 7+ years of relevant work experience. Or a Master's in the same fields with 5+ years of relevant work experience. Or a PhD in the same field with 2+ years of relevant work experience.
    Your experience must be in the following:
    
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      SOC design methodology, IP/SOC integration, floor planning, synthesis tools and methodology and a self-driven candidate with deep knowledge of SOC design delivery with a proven track record of successful tape-ins on Intel technology along.
      
      
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      Physical design flows (RTL2GDS, analysis and signoff tools).
      
      
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      Experienced in Synopsys and other vendor tool flow methodology including Syn, APR, Timing closure (Primetime), Noise analysis, Reliability and LVS/DRC closure.
      
      
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      IP Design collateral handoff, QA and integration/handoff process process.
      
      
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      Scripting languages (e.g. Perl, Python, Shell, etc.).
      
      
      This is an Intel Federal Position
      Inside this Business Group
      The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center. Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.
      Covid Statement
      Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
      Posting Statement
      All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
      Benefits
      We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
      Working Model
      This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Keywords: Intel, Trenton , SOC Senior Physical Design Manager, Executive , Trenton, New Jersey